1. Field of the Invention
This invention relates generally to the field of data communications within a multiprocessor computer system, and particularly to a technique for optimizing the memory response time of a shared memory system utilizing a split transaction bus for burst data transfers.
2. Background Art
Modern data processing systems typically include a main memory system constructed with dynamic random access memory (DRAM) devices. The main memory system communicates by way of a memory bus or system bus with other agents of the system such as processors and direct memory access (DMA) masters. A memory controller directs data into and out of the main memory system. High performance systems with multiple processing units require a greater bandwidth on the memory bus to handle the multiple memory access requests generated by the multiple processing units.
One technique for increasing the effective bus bandwidth required in multiprocessor systems is the use of a split transaction bus. In a split transaction, an agent of the system requests a memory access, thereby initiating a transaction, and the transaction is completed when the requested data is supplied by the memory system. In the interval between the memory request and the transfer of data fulfilling the request, the memory bus is available for other transactions. While this technique increases the effective bandwidth of the memory bus, it does so at the expense of longer latencies. If a multiprocessor system is configured with only a single processor, a split transaction bus actually degrades performance of the system due to the increased latencies which could be avoided by using a simple shared memory bus.
At the present time, there are relatively few operating systems and applications programs that exploit the power and performance of a multiprocessor system. Thus, a multiprocessor system will frequently operate in a uniprocessor mode. For example, a system that is multiprocessor (MP) ready for OS/2 or UNIX will operate in a uniprocessor mode when running DOS. Therefore, it is desirable that a multiprocessor system be designed to optimize bus performance in a uniprocessor mode as well as a multiprocessor mode.
As mentioned above, a simple shared memory bus minimizes memory access latencies in a uniprocessor environment. FIG. 1 illustrates the sequence of events for a single transaction on a simple shared memory bus. A read request is issued by a requesting agent and transmitted on the memory bus. The request is received by the memory controller and decoded to generate the control signals that retrieve the requested data from the memory. The data is then transmitted on the memory bus to the requesting agent. The bus is occupied for the entire time of the transaction from the initiation of the read request to the completion of the data transmission. No bus arbitration is required since the bus is owned by the requesting and responding agents for the duration of the transaction. Thus, access to the bus is denied to all other agents in the system.
Operation of a typical split transaction bus is illustrated in FIG. 2. A transaction is similarly initiated by a read request from a requesting agent. As in a simple shared bus implementation, the read request is received by the memory controller which decodes the request and generates the memory access control signals. However, unlike the simple shared bus, the split transaction bus is occupied only during the time that the read request is transmitted. The bus is then made available to other agents while the request is decoded and requested data is retrieved from the memory. The retrieved data is typically stored in a first in, first out (FIFO) data buffer until the bus is again available to transmit the data to the requesting agent. When the data is available for transfer, a bus arbitration and grant sequence arbitrates active bus access requests from other requesting and responding agents and then assigns the bus to the responding agent to transmit the data to the requesting agent. As can be seen, bus availability is increased, but memory response latency is also increased due to the sequential nature of the memory read, memory bus arbitration, bus grant and data transmission operations. Of course, such increase in latency could be avoided by sending the accessed data directly onto the memory bus as it is retrieved from the memory; however, this would require that access to the bus be denied to other agents prior to and during the time that the data is retrieved in order to avoid bus collisions. Such an approach would therefore negate most of the increase in bandwidth achievable with the split transaction technique.